Marvell OCTEON 10 CN102 vs. CN103: The DPU Selection Guide for Enterprise Networks
Marvell OCTEON 10
CN102
The cost-efficient workhorse for 10G deployments
VS
Marvell OCTEON 10
CN103
The high-throughput platform built for 25G and beyond
Why DPUs Are Now Essential
In recent years, a fundamental shift has taken place across the networking landscape. The rapid adoption of cloud computing, 5G, and edge computing has transformed networks from mere connectivity infrastructure into the core foundation for business workloads, distributed computation, and security policy enforcement. In this new reality, traditional CPU-centric architectures are increasingly struggling to keep pace.
The issue is not that CPUs lack processing power — it is that they are being used for the wrong tasks. In many systems, a significant share of expensive CPU cycles are consumed not by business applications, but by infrastructure-level operations such as:
- Packet processing and forwarding
- Encryption and security offload (IPsec, TLS, and other compute-intensive workloads)
- Virtual switching and overlay networking
- Traffic inspection and telemetry
When network speeds were still in the 10G era, these overheads were manageable. But as bandwidth scales to 25G, 100G, and beyond, the computational burden of these tasks grows exponentially — rapidly becoming the primary bottleneck of the entire system.
This is precisely where the Data Processing Unit (DPU) enters the picture. The principle is straightforward: offload these heavy, infrastructure-intensive tasks from the CPU and hand them to purpose-built hardware accelerators. The results are direct and measurable: higher throughput and lower latency, superior power efficiency at equivalent performance levels, and greater system scalability.
To put it plainly: the value of a DPU is not to replace the CPU, but to liberate it — allowing it to focus on business logic rather than being taxed by networking and security overhead.
Cutting Through the Noise: What CN102 and CN103 Share
With DPU value established, let us examine two of today’s most representative products: Marvell OCTEON CN102 and Marvell OCTEON CN103. First-time evaluators of these two chips often arrive at the same question: “The core count and architecture look identical — so what exactly is the difference?”
That is precisely the right question, because the answer is critical. If raw compute is your only lens, the two chips appear nearly equivalent.
Both belong to the next-generation Octeon 10 platform:
- TSMC 5nm process technology
- Up to 8-core Arm Neoverse N2 CPU complex
- DDR5 memory support
- Integrated hardware acceleration for cryptography, networking, and ML inference
In performance and power efficiency, both deliver approximately 3× throughput improvement with a 50% reduction in power consumption compared to prior generations. In short, their computational “brains” operate at the same fundamental level. So where does the real difference lie?
Network Bandwidth: The Core Distinction: I/O Capability Defines the Ceiling
The answer lies in a single, critical dimension: I/O bandwidth.
Think of a chip as a modern high-throughput city: the CPU is the manufacturing district — an enormously productive industrial engine. The I/O subsystem is the city’s road and rail network. No matter how productive the factories, if the transport infrastructure cannot move goods fast enough, output stagnates at the city limits. The fundamental divergence between CN102 and CN103 comes down to exactly this: who built the wider roads.
How Fast Can Data Leave the Device?
Many engineers default to CPU core count when evaluating network silicon, but in real-world network-facing deployments, the true throughput ceiling is determined by the SerDes tier — the high-speed serializer/deserializer interfaces that govern maximum data ingress and egress rates.
CN102 · SERDES
10G
SerDes
A robust and proven lane for traditional network environments supporting 1G through 10G interfaces.
Interfaces: 4×10G + 2×10G
CN103 · SERDES
56G
SerDes
A generational leap — full backward compatibility with 10GbE while natively supporting 25G, 50G, and aggregated 100G deployments.
Interfaces: 4×50G/25G/10G + 2×10G
The selection checkpoint is simple: Is your target platform designed for the 10G era, or does it need to scale into 25G territory and beyond? That single answer eliminates half the decision.
PCIe Expansion: Will the Internal Data Fabric Keep Up?
If SerDes defines the external interface ceiling, PCIe generation determines whether the internal data fabric can sustain it.
CN102
PCIe 3.0
A well-matched configuration for compact, closed-form-factor devices that do not require external acceleration cards. Delivers exactly the throughput needed, with no unnecessary cost overhead.
CN103 · SERDES
PCIe 5.0
Double the available bandwidth, providing future headroom for attaching SmartNICs, AI inference accelerators, or high-speed NVMe storage.
Even with 100G front-panel ports, a constrained PCIe bus will create an internal bottleneck that prevents the full interface capacity from ever being realized.
This is why the two chips are purpose-built for fundamentally different roles: CN102 is purpose-optimized for streamlined, cost-efficient, fixed-form-factor 10G platforms; CN103 is the architectural foundation for high-performance, expandable, future-proof systems.
Which One Should You Choose?
The right selection is not about which chip is “better” in absolute terms — it is about which one is right for the problem you are solving.
RIGHT CHOICE WHEN →
Performance Is Sufficient,
Cost Efficiency Is Critical
Typical target platforms
→ Enterprise CPE / uCPE gateways
→ Entry-to-mid-range firewalls
→ Standard SD-WAN appliances
→ Small-scale 5G edge devices
→ Switch control plane processors
Shared characteristics
→ Interface requirements at or below 10G
→ High sensitivity to unit cost and power consumption
→ No requirement for complex PCIe expansion
Summary: For high-volume, cost-sensitive deployments, CN102 is the optimal choice — delivering the full capabilities of a next-generation DPU platform at the lowest possible system cost.
RIGHT CHOICE WHEN →
Bandwidth and Longevity
Are the Priority
Typical target platforms
→ 25G / 100G firewalls
→ High-end SD-WAN / SASE platforms
→ 5G User Plane Function (UPF) nodes
→ SmartNIC and DPU acceleration cards
→ SmartNIC / DPU accelerator cards
→ High-performance edge computing nodes
Shared characteristics
→ High-speed interface requirements (25G / 100G)
→ Potential need for PCIe expansion with accelerator or storage cards
→ Extended product lifecycle expectations
Summary: For platforms designed around a three-to-five year roadmap, CN103 is the only rational choice. Beyond raw performance, its architectural headroom ensures the platform remains relevant throughout its service life.
A Three-Step Selection Framework
1
What’s the highest
interface speed your
device needs to support?
→ ≤ 10GbE → CN102
→ 25G or higher → CN103
2
Will you need to attach
expansion cards (SmartNIC,
AI accelerator, NVMe)?
→ No expansion needed → CN102
→ Yes, or maybe later → CN103
3
Is this a cost-sensitive
mass deployment, or a
long-lifecycle flagship?
→ Mass / cost-optimized → CN102
→ High-end / long lifecycle → CN103
Specification Comparison
| Specification | Marvell OCTEON 10 CN102 | Marvell OCTEON 10 CN103 |
|---|---|---|
| Product Positioning | Cost & power optimized | High throughput + expansion |
| CPU Architecture | Up to 8-core Arm Neoverse N2 | Up to 8-core Arm Neoverse N2 |
| Manufacturing Process | TSMC 5nm | TSMC 5nm |
| Memory | DDR5 | DDR5 |
| SerDes Speed | 10G SerDes | 56G SerDes |
| Network Interfaces | Up to 4×10G + 2×10G | Up to 4×50G/25G/10G + 2×10G |
| PCIe Generation | PCIe 3.0 (up to 6 controllers) | PCIe 5.0 (up to 6 controllers) |
| Hardware Acceleration | Inline Crypto, VPP, ML inference | Inline Crypto, VPP, ML inference |
| Typical Chip TDP | 10–20W | 10–25W |
| System Throughput | ~50 Gbps class | 100 Gbps+ class |
| Crypto Performance | ~50 Gbps | ~80 Gbps |
| Power Consumption | Lower (~60W system) | Higher, significantly more capable |
| Core Use Cases | Enterprise gateways, entry-to-mid-range firewalls, standard SD-WAN, branch edge devices | 25G/100G firewalls, high-end SD-WAN/SASE, 5G UPF nodes, high-performance edge computing |
Asteraix’s Open Gateway Lineup
Understanding the chip is step one. Getting hardware that actually ships with Linux-ready firmware, open NOS support, and commercial warranty is a different challenge entirely. Asteraix has built white-box gateway appliances on both OCTEON 10 platforms — fully open, ready for Debian/Ubuntu or AsterNOS-VPP out of the box, without vendor lock-in.
CN102-Based: ET2508 Open Intelligent Gateway
10G-class · Arm Neoverse N2 · Inline crypto · PoE+ optional
ASTERAIX ET2508
8-Core Arm Neoverse N2 Open Intelligent Gateway
4×10GE + 2×10GE · Optional PoE+ / PoE++
4× M.2 slots (SSD or crypto engine) · Inline crypto engine
Debian / Ubuntu / AsterNOS-VPP · DPDK · SONiC
CN103-Based: ET3608 & ET3616 Open Gateways
25G/50G-class · PCIe 5.0 · High-throughput SASE & UPF
ASTERAIX ET3608
ET3608-2P2S Open Gateway — Marvell CN103
56G SerDes · PCIe 5.0 · 4×50G/25G/10G + 2×10G
Ideal for SD-WAN / SASE edges, 5G UPF, high-end firewalls
Debian / Ubuntu / AsterNOS-VPP · SONiC
ASTERAIX ET3616
ET3616-4P4S Open Gateway — Marvell CN103
56G SerDes · PCIe 5.0 · Higher port density
Aggregation nodes, high-capacity edge compute
Debian / Ubuntu / AsterNOS-VPP · SONiC
Software: Open by Design, Defined by You
The hardware is only the foundation. Asteraix’s most distinctive advantage is its fully open software ecosystem:
Native Linux Support
Both DPU white-box appliances support standard Debian / Ubuntu installations out of the box. Deploy your own applications, containers, and microservices directly — just as you would on a standard Linux server — enabling low-cost, purpose-built network security appliances built on your own software stack..
AsterNOS-VPP (Open Router OS)
For enterprises requiring a production-grade, plug-and-play routing and forwarding platform, AsterNOS-VPP is Asterfusion’s purpose-built operating system. Deeply integrating SONiC’s open architecture with VPP (Vector Packet Processing) technology, and leveraging Marvell OCTEON 10’s onboard hardware VPP acceleration engine, AsterNOS-VPP maximizes packet forwarding throughput and concurrent connection capacity for demanding enterprise gateway and complex routing environments. Full support for BGP and OSPF dynamic routing, IPsec VPN, NAT, ACL, QoS, and comprehensive traffic telemetry — all delivered with ASIC-grade line-rate forwarding performance on top of a fully flexible Linux foundation.
Between CN102 and CN103, the question is never “which is more powerful” — it is always “which solves your problem.” Need cost-effective 10G deployment at scale? CN102. Need high-throughput, high-bandwidth performance built for the next five years? CN103.