Teralynx 10 is Marvell’s 51.2 Tbps programmable Ethernet switch ASIC for next-generation cloud, AI/ML, and HPC fabrics. Built on a clean-sheet architecture in 5 nm, it targets top-of-rack, leaf, spine, super-spine, and AI cluster roles where bandwidth, radix, and latency all matter.
Capacity and port flexibility
- Up to 51.2 Tbps switching capacity with 512 × 112G long-reach SerDes.
- Typical high-density designs: 64 × 800GbE, 128 × 400GbE, or 512 × 100GbE.
- 200 MB+ on-chip packet buffer for burst absorption and RoCE-friendly congestion control.
Performance positioning
- Ultra-low latency: Marvell cites latency from ~500 ns and sub-600 ns across packet sizes; Asteraix 800G platforms built on Teralynx 10 target sub-560 ns port-to-port latency.
- Programmable forwarding with in-field feature updates for evolving AI protocols and telemetry (including INT-style visibility).
- Optimized for GPU/AI training and inference, NVMe-oF storage fabrics, and distributed workloads where job completion time depends on network delay.
At Asteraix
With Marvell Teralynx 10 at its core, Asteraix 800G switches deliver line-rate 51.2 Tbps fabrics with sub-560 ns latency—built for AI/ML, HPC, and NVMe workloads where speed drives results.