A data center switch is a high-performance network device designed to interconnect servers, storage, and other networking equipment inside a data center at speeds from 25G to 800G. Unlike campus switches, data center switches prioritize ultra-low latency, high port density, non-blocking throughput, and advanced automation — often running open network operating systems like SONiC.
Data Center Switch Architecture: Leaf-Spine
Modern data centers are built on leaf-spine (also called Clos) architecture. Understanding this is essential to understanding where data center switches live:
Leaf switches (ToR — Top of Rack): connect directly to servers. Every server in a rack connects to its leaf switch at 25G or 100G. Leaf switches are the access layer.
Spine switches: interconnect all leaf switches. Every leaf connects to every spine at 100G, 400G, or 800G, creating a fully non-blocking fabric. Spine switches carry east-west traffic between racks.
Super-spine (for very large deployments): a third tier connecting multiple spine planes in a multi-pod architecture.
This flat architecture delivers equal bandwidth between any two servers in the fabric, eliminating bottlenecks common in legacy three-tier (access/distribution/core) designs.
Types of Data Center Switches by Speed
| Speed tier | Typical role | Common use case |
| 25G | Leaf / ToR — server access | Standard server NIC connections in general compute clusters |
| 100G | Leaf or spine | High-density server access or moderate-scale spine fabric |
| 200G | Spine / inter-rack | Mid-scale spine fabric, storage networking |
| 400G | Spine / core | Large-scale data center spine, hyperscale deployments |
| 800G | Ultra-high-density spine | AI/ML GPU cluster interconnect, next-generation hyperscale |
Key Specifications to Evaluate
Switching capacity (Tbps): total bandwidth the switch can move simultaneously. A 32-port 400G switch has 12.8 Tbps of capacity if non-blocking.
Latency: critical for HPC, AI training, and financial trading. Look for cut-through forwarding mode which achieves ~200–500ns vs store-and-forward at several microseconds.
ASIC chipset: determines features and performance. Key chipsets include Broadcom Tomahawk series (high performance), Marvell Teralynx (low latency, AI networking), and Marvell Falcon.
Buffer size: larger buffers absorb traffic bursts and prevent packet drops in congested east-west flows — critical for AI/ML workloads.
Power consumption and cooling: high-port-density switches can consume 500W–2,000W+. Consider airflow direction (front-to-back or back-to-front) for data center hot/cold aisle containment.
NOS compatibility: ensure the switch supports your chosen network OS — SONiC, Cumulus, or vendor-proprietary.
Data Center Switches for AI and ML Workloads
AI/ML training clusters have unique networking requirements that differ from traditional data centers:
All-to-all communication patterns: GPU-to-GPU collective operations (AllReduce, AllGather) require every GPU to communicate with every other GPU simultaneously — demanding non-blocking, low-latency fabrics.
RoCE (RDMA over Converged Ethernet): AI workloads use RoCE v2 to move tensor data directly between GPU memory over Ethernet without CPU involvement. Switches must support Priority Flow Control (PFC) and ECN for lossless Ethernet.
High port density at 400G/800G: a single rack of 8 H100 GPUs generates 800G of traffic — spine switches must match this bandwidth.