Teralynx 7 is Marvell’s programmable Ethernet switch ASIC family for 100G–400G cloud and AI data-center networks. Devices scale from 3.2 Tbps to 12.8 Tbps (for example IVM77310 and IVM77700), sharing a low-latency fabric architecture aimed at leaf, spine, and top-of-rack deployments.
Capacity and port flexibility
- Up to 12.8 Tbps on the flagship die, with large on-chip buffers (on the order of 70 MB in typical 12.8T designs).
- High-density port maps include 32 × 400GbE, 64 × 200GbE, 64 × 100GbE, and 32 × 100GbE, with backward-compatible 10G–100G breakout modes.
- 50G PAM4 SerDes enable cost-efficient 200G and 400G connectivity in 1U–2U form factors.
Performance positioning
- Ultra-low latency around ~500 ns class—suited to AI training clusters, HPC, financial trading, and latency-sensitive spine layers.
- High packet forwarding rate and deep buffers vs. many 3.2T-class alternatives, improving burst tolerance for RoCE and east-west traffic.
- Strong fit for flat leaf–spine CLOS fabrics, super-spine aggregation at 400G, and SONiC/open-NOS platforms where throughput per watt matters.
How it differs from Teralynx 10
Teralynx 7 covers the 100G–400G generation (up to 12.8 Tbps). Teralynx 10 extends the same architectural philosophy to 800G and 51.2 Tbps for AI-scale backend networks. Choose Teralynx 7 for dense 100G/200G/400G leaf and spine; choose Teralynx 10 when the fabric must scale to 800G GPU interconnect.
At Asteraix
Asteraix AI RoCE Fabric switches from 32 × 100G through 32 × 400G are built on Marvell Teralynx 7—including the CX532P-N (3.2 Tbps), CX732Q-N (12.8 Tbps), CX664D-N, and CX564P-N platforms for leaf, spine, and ToR roles in RoCEv2 AI/HPC fabrics.